The present invention claims the benefit of Korean Patent Application No. P20000067154 filed in Korea on Nov. 13, 2000, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a liquid crystal display panel, and more particularly, to a liquid crystal display (LCD) panel with low resistance interconnections.
2. Discussion of the Related Art
In order to provide an active matrix type LCD panel having a high precision, a large size, and a wide aperture, it is essential that the signal lines of a TFT (Thin Film Transistor) in the LCD panel (i.e., the gate and the data lines of the TFT) be thin and lengthy. Moreover, for eliminating wave distortion of a pulse signal, it is preferable to have low resistance interconnections for the LCD panel. Metals such as gold, aluminum, copper, and platinum are generally used as materials for LCD panel interconnections. A related art process for fabricating a TFT in an LCD panel using one of the foregoing single metals is explained below.
In the process to form gate lines, gate electrodes, and gate pads of the TFT array in the LCD panel, a metal, such as copper, is sputtered on a transparent substrate and thereafter subjected to a photo process and wet etching (by chemical). After the gate lines, the gate electrodes, and the gate pads are formed, a gate insulating film of SiNx, or the like, is formed on the surface of the transparent substrate that includes the TFT-array part and the gate pad part, by PECVD (Plasma Enhanced Chemical Vapor Deposition).
A semiconductor layer of a-Si or the like and an impurity-doped semiconductor layer of n+a-Si or the like are deposited on the gate insulating film by PECVD, and thereafter patterned to leave the semiconductor layers on a TFT forming region (i.e., the TFT-array part) over the gate electrodes, thereby forming an active layer and an ohmic contact layer of the TFT array.
A metal, such as copper, is deposited on the surface of the substrate and thereafter selectively removed to form data lines and source/drain electrodes of the TFT array. The data lines, together with data pads, are formed to cross the gate lines. Then, the ohmic contact layers between the source and drain electrodes are removed selectively by using a mask for the source/drain electrodes.
After a protection film is formed on the substrate surface that includes the data lines and the source/drain electrodes, the gate insulating film and the protection film formed on the gate pad parts are removed by wet etching with chemicals to expose a region of the gate pads. Also, the protection film over the drain electrodes is removed selectively to form contact holes. The protection film on the data pads is similarly removed by wet etching with chemicals to expose a region of the data pad.
Then, ITO (Indium Tin Oxide) is sputtered, and wet etched, to form a transparent conductive film on each gate pad and data pad such that the transparent conductive film is in contact with both the gate pad and the data pad. At the same time, a pixel electrode connected to the drain electrode is formed in each pixel region in the TFT array.
However, the foregoing prior art method for fabricating an LCD panel has the following problems.
As the interconnection metal is in the form of a thin film of polycrystalline grains, the grain boundaries between the grains in an aggregate of the polycrystalline grains are non-crystalline. A non-crystalline grain boundary is susceptible to electricity and chemical that distort intrinsic characteristics of the grain boundary and thereby alter properties (e.g., electrical properties) of the interconnection metal. For example, a copper interconnection with non-crystalline grains becomes susceptible to acid so as to exhibit the distortion caused by CuO present at the grain boundary. Therefore, it has been very inconvenient to prepare a separate TFT-array fabrication process since an interconnection of the TFT-LCD using such copper containing CuO at a grain boundary of a crystal is susceptible to chemical and moisture.
Problems with a copper interconnection susceptible to chemical are explained in detail with reference to FIG. 1, which illustrates a reaction in wet etching of copper interconnections in a related art LCD panel. FIG. 1 shows that the CuO at the grain boundary of a polycrystalline copper thin film is exposed to chemicals to initiate corrosion at the grain boundary and develop the corrosion along the grain boundary of the crystalline grain. As properties (e.g., electrical properties) of the copper thin film are distorted significantly due to the corrosion, the properties of the copper interconnection are substantially deteriorated.
In the fabrication process of a TFT-array which drives unit pixels, the etching of ITO (Indium Tin Oxide) used as pixel electrodes and gate and data lines, and the etching of silicon oxide or silicon nitride used as an insulating layer or protection layer is required. As such an etching is generally performed by introduction of certain chemicals that produce salt or ion continuously based on their chemical reactions during the etching process, the properties of these chemicals are susceptible to change over time. If such an etching chemical infiltrates into an interconnection, that chemical is likely to develop corrosion of the interconnection instantly. Also, because the interconnection of copper is susceptible to moisture, corrosion can be developed at the copper interconnection due to any change in the pH during the course of washing the chemical. For example, because an ITO etchant comes into contact with the gate lines under the ITO when the ITO electrodes are patterned to form the pixel electrodes, if the gate lines are not resistant to the ITO etchant, the gate lines may get broken or cracked due to corrosion. Therefore, the reaction between the chemical (etchant, or stripper) used in wet etching and the CuO needs to be taken into account during the LCD panel fabrication, and a specific chemical should be prepared based on the reaction information. However, even if the composition of the etching chemical is adjusted, the process tolerance still remains small and the process stability low.
Thus, in order to solve the problem of copper being susceptible to chemical and moisture, a copper alloy, rather than pure copper, may be used. However, even if the copper alloy is used during fabrication of LCD panel interconnections, the copper alloy with more than 1% of non-copper content may deteriorate electrical conductivity. This is undesirable because good electrical conductivity is supposed to be the greatest advantage of pure copper.
Accordingly, the present invention is directed to a TFT array in an LCD panel that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
In one embodiment, the present invention provides a copper alloy that includes a copper portion and a metal portion doped in the copper portion. The metal portion in the copper alloy includes a metal whose heat of metal oxide formation energy is greater than that of copper. In one embodiment, the metal is one selected from Ti (Titanium), Cr (Chromium), Ta (Tantalum), Mo (Molybdenum), In (Indium), Sn (Tin) and Al (Aluminum). The doping concentration of the metal portion is in the range of 0.001% to 0.1% of the copper portion.
In another embodiment, the present invention provides a thin film transistor (TFT) array and an LCD panel made therefrom where at least one of the gate lines, the source electrodes, the drain electrodes and the data lines is formed of the copper alloy according to the present invention.
The formation of a metal oxide of an alloy of copper that is doped to a required amount at a grain boundary of crystalline copper with a metal whose heat of metal oxide formation energy is greater than that of copper permits to reduce corrosion of interconnections caused by wet etching during fabrication of a TFT array for an LCD display panel. The copper alloy has a high acid resistance, a high chemical resistance, and a high tolerance for moisture. The use of the copper alloy according to the present invention prevents damage to the interconnection during and after fabrication of the TFT array, and allows formation of a low resistance interconnection of copper that has a high electrical conductivity.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.